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特斯拉公布新版超级智能(SI)加速器路线图:AI4、AI5、AI6更名为SI4、SI5、SI6,第六代推理芯片SI6目标算力为现款80倍、内存9倍,Dojo D3改用芯粒加堆叠HBM

2026-11-08 · 科技 · GSM News
特斯拉公布新版超级智能(SI)加速器路线图:AI4、AI5、AI6更名为SI4、SI5、SI6,第六代推理芯片SI6目标算力为现款80倍、内存9倍,Dojo D3改用芯粒加堆叠HBM

据 Tom's Hardware 11 月 6 日报道,特斯拉(Tesla)公布了新版超级智能(SI)加速器路线图,并把芯片命名体系整体更换:原称 AI4、AI5、AI6 的三代推理芯片,现统一改称 SI4、SI5、SI6。报道称,特斯拉此次采用「超级智能」(super intelligence,缩写 SI)这一表述为其加速器命名。

路线图的核心数字落在第六代推理加速器 SI6 上。按特斯拉在演示材料中给出的目标,SI6 的计算性能约为现款第四代芯片的 80 倍,内存容量约为 9 倍。需要说明的是,特斯拉并不公布现款芯片的绝对算力数值,因此外界流传的绝对算力区间系以第四代芯片的估算值为基数推算,并非特斯拉公布的官方数字。

训练芯片方面,新版路线图显示,Dojo 训练加速器的下一代产品 D3(Dojo 3)将放弃此前以 SRAM 为中心的设计,改用多芯粒(chiplet)架构并堆叠高带宽内存(HBM)。报道称,特斯拉尚未披露 D3 的算力、内存容量、制造工艺与上市时间表。

Tom's Hardware 的报道指出,这份路线图给出了特斯拉自研芯片未来数年的方向:车端与数据中心推理继续沿 SI 系列迭代,训练侧则以全新架构的 D3 重新出发。上述性能目标与时间安排均属特斯拉演示材料中的规划表述,尚非已量产产品的实测结果。

Tesla Unveils Revised SI Accelerator Roadmap: AI4, AI5 and AI6 Renamed SI4, SI5 and SI6, Sixth-Generation SI6 Inference Chip Targets 80 Times the Compute and Nine Times the Memory of the Current Chip, Dojo D3 Moves to Chiplets With Stacked HBM

Tesla has disclosed a revised artificial-intelligence accelerator roadmap and renamed its chip line, according to a November 6 report by Tom's Hardware based on Tesla presentation materials. The three generations of inference chips previously called AI4, AI5 and AI6 are now labeled SI4, SI5 and SI6, under what the report describes as a "super intelligence" branding push.

The headline figure in the roadmap concerns the sixth-generation inference accelerator, the SI6. Per Tesla's presentation, the SI6 is expected to deliver about 80 times the compute performance of the existing fourth-generation chip, and about nine times the memory. Tesla does not publish the current chip's absolute compute performance, so absolute performance ranges circulating in coverage are estimates derived from an estimated baseline, not figures Tesla has officially disclosed.

On the training side, the roadmap shows the next Dojo training accelerator, D3 (Dojo 3), dropping its earlier SRAM-centric architecture in favour of a multi-chiplet design with stacked high-bandwidth memory (HBM). Tesla has not disclosed D3's compute performance, memory capacity, manufacturing process or launch schedule, according to the report.

Tom's Hardware said the roadmap sheds light on the future of Tesla's in-house chip development: inference continues along the SI series, while training restarts on an entirely new D3 architecture. The performance targets and timing in the presentation are Tesla's stated plans, not measured results from production hardware.

来源:Tom's Hardware

发布:GSM·美国(发布链接)

图片来源:图:特斯拉标识。图片来源:GSM资料图。 / Photo: The Tesla logo. Source: GSM file photo.

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